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None scheduled at this time.

Note - We reserve the right to cancel courses because of low enrollment.


The explosive growth in Chemical-Mechanical Polishing for planarizing VLSI circuits has resulted in a high demand for equipment, consumables, and process technology. The lack of trained and experienced personnel is a critical issue to the industry. At the same time, newcomers to the field can experience considerable difficulty in coming up to speed as they attempt to understand how an old process has been adapted for a new high technology application. It is the purpose of this three-day intensive short course to provide an introduction to the technology of Chemical Mechanical Planarization using an approach which combines key CMP principles with practical equipment and process information.

Using a combination of lecture presentations and hands-on laboratory demonstrations, the focus of the course is on the technology and manufacturing aspects of the CMP process, including process parameters and controls, consumable materials, equipment types, and characterization of planarized wafers. Background information on IC processes and materials which are directly related to the need for CMP will also be included, such as lithography, thin film deposition processes, multilevel metal and insulator properties, and etching.

Who Should Attend

This course is intended for persons who are interested in learning about the practical details of CMP technology. Accordingly, individuals working in CMP-related areas of process engineering, technical sales, equipment design, manufacture of consumables and technical management could benefit from the course, as well as those who are interested in evaluating the technology for future use or commercialization. Participants should have understanding of introductory physics and chemistry. Although familiarity with microelectronic fabrication may be helpful, it is not assumed, and there will be abundant opportunity to tour the RIT clean room and view the I.C. processing equipment set.


The first part of the course explains why planarization has become so critical to certain VLSI circuits. It discusses the driving forces and the reasoning leading to the use of CMP. This is followed by a fundamental description of polishing as it is understood from early studies on glass, and more recent information on polishing of silicon wafers. The basic differences between polishing and abrasive finishing, between conventional polishing and CMP, and between pure chemical and pure mechanical removal are discussed.

The course also introduces Multilevel Interconnect (MIC) structures and the I.C. fabrication processes which are typically integrated with CMP, such as deposition methods for metals, dielectrics, and adhesion/barrier layers, lithographic technology, and etching. Relevant properties of the various materials are discussed such as metal resistivity, dielectric constant, and contact resistivity. Other related properties such as film stress, adhesion, crystallinity, and purity are covered.

CMP technology is covered in detail starting with consumables; (pads and slurries), process; (pressure, pad speed, temperature, pad wear and conditioning, pattern density effects), manufacturing concerns; (endpoint detection, selectivity, polish stop layers, post-CMP cleaning), and evaluation and characterization; (dishing, erosion, profilometry, microscopy, defect detection).


The laboratory portion of the course includes CMP of blanket films and patterned dielectric/metal structures. Characterization methods include film thickness measurements for removal rate and within-wafer non-uniformity, topographical profile using atomic force microscopy and stylus profilometry, and defect detection with optical and scanning electron microscopy. Related I.C. processing steps include thin film deposition, micro-photolithography, and plasma etching.


The Center for Microelectronic and Computer Engineering features more than 15,000 sq.ft. of class 10-100-1000 cleanroom. Integrated circuit and maskmaking equipment worth more than $20 million provides for state-of-the-art processing of I.C.s. This includes HP workstations with Mentor Graphic design tool, Silvaco process simulation tools, Oxidation and Diffusion Furnaces, Steppers (g-line, I-line, DUV, 193nm), Sputtering systems, Plasma Etch and IBM AS/400 Computer network for work-in-progress tracking.


First Day

  • Registration and Coffee
  • Overview of Microelectronic Engineering at RIT
  • CMP Market: History and Growth
  • Why CMP? - The Driving Forces
  • Multilevel Interconnect Structures
  • Background and Principles of CMP
  • Lunch
  • Multilevel Interconnect Materials
  • Laboratory Demonstrations
  • CMP of Blanket Oxide
  • Film Thickness Measurements
  • Microlithography

Second Day

  • CMP Equipment and Consumables
  • Microlithography
  • CMP Processes and Technology
  • Lunch
  • Plasma Etching
  • Laboratory Demonstrations
  • CMP of Patterned Structures
  • Profilometry
  • Atomic Force Microscopy
  • Plasma Etching

Third Day

  • CMP Process Parameters and Controls
  • Characterization and Post-CMP Cleaning
  • Depositiong Techniques for Dielectrics and Metals
  • Trends and the Future
  • Lunch
  • Laboratory
  • Demonstration of Scanning Electron Microscope (SEM)
  • Tour of Facility
  • Wrap-up
  • Course Evaluation and Award Certificates
  • Adjourn