Secure Neuromemristive Primitives for SHA-3

Security depends on the implementation of cryptographic systems that take into account cryptographic algorithmic weakness and the weaknesses of the devices they are implemented on. The algorithm can be strong but if the implementation hardware leaks information, this could give enough information to a hacker to correlate the leaked data to the input data. Once a correlation can be made from power/timing/radiation/other data to the input data, the data can then be seen as compromised.

The dominant design medium currently is complementary metal-oxide semiconductor (CMOS). CMOS has been analyzed to leak more power as the technology node sizes decrease. The leaked power has been shown to have a strong correlation with the bits being manipulated in a device. These power leakages have brought on a class of power analysis that is able to extract intended secret information with far less computer power then brute force guesses. Recently, many hardware designs have been proposed which have shown resistance against different forms of power analysis by using different hardware layouts. These designs have been show to drastically reduce the effectiveness of power analysis as the amount of work to do the attacks increases to the complexity of the attack taking too long to be feasible. However, these technologies that are introduced are based in the same technology, CMOS, that has caused the side channel attack problem in the first place. This means that as the attacks become more effective, these countermeasures might not be able to hold up anymore.

There are many emerging technologies that are becoming more practical to implement in circuit design. Of these, neuromemristive devices seem to have two characteristics that could be exploited to prevent proper power analysis, low power operation and stochastic power consumption. In this project, an attack will be implemented on both a CMOS implementation of Keccak and a neuromemrisitve implementation. Metrics such as success rate, confidence ratio, and number of powers traces, for the Correlation Power Analysis (CPA) attack on the CMOS implementation and a neuromemristive implementation, will be used to verify and validate the increase in security protection. Verilog AMS, VHDL, Python and Matlab will be used for testing platform.


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