Dr. Sonia Lopez Alarcon received a B.S. in Physics and M.S. Electronics in from the University Complutense of Madrid, Spain. In her latest college years she worked at Lucent Technologies, Madrid, and Fundetel at Polytechnic University of Madrid, where she became familiar with the design and fabrication process of integrated circuits. In 2003 she started working toward a PhD degree in Computer Engineering at the University Complutense of Madrid, focusing on cache hierarchy in simultaneous multithreaded architectures. In 2004 she started her cooperative research with Professor David H. Albonesi, at the University of Rochester and, later on, at Cornell University. She graduated in 2009, and she joined the Department of Computer Engineering at the Rochester Institute of Technology in the fall of 2009. Her current research interest is on cache optimization, GPU architecture, and heterogeneous hardware solutions.
- A phase adaptive cache hierarchy for SMT processors. S. Lopez O. Garnica. D. H. Albonesi, S. Dropsho, J. Lanchares, J. I. Hidalgo. Microprocessors and Microsystems, 2011
- Reducing Power of Functional Units in High-Performance Processors by Checking Instruction Codes and Resizing Adders. G. Miñaña, J.I. Hidalgo, J. Lanchares, J.M. Colmenar, O. Garnica and S. López. IET Computer & Digital Techniques, 2007
- A Comparison of Sequential and GPU-Accelerated Implementations of B-Spline Signal Processing Operations for 2-D and 3-D Images. A. Karantza, S. Lopez and N. D. Cahill. International Conference on Image Processing Theory, Tools and Applications, October 2012
- GPU Acceleration of Transmural Electrophysiological Imaging. M. Corraine, S. Lopez, L. Wang. Computing in Cardiology, September 2012
- Low bandwidth eye tracker for scanning laser ophthalmoscopy. Z. Harvey, A. Dubra, N. cahill. S. Lopez. SPIE Medical Image, February 2012
- Efficient resource management for Cloud computing environments.A. J. Younge, G.von Laszewski, L. Wang, S. Lopez Alarcon, W. Carithers. Green Computing Conference, August 2010
- Adaptive Cache Memories for SMT Processors. S. Lopez O. Garnica. D. H. Albonesi, S. Dropsho, J. Lanchares, J. I. Hidalgo. Euromicro conference on Digital system Design, 2010
- Improving SMT Performance: an Application of Genetic Algorithms to Configure Resizable Caches. J. Díaz and J. Ignacio Hidalgo and Francisco Fernández and Oscar Garnica and Sonia López. Late-Breaking Paper, Genetic and Evolutionary Computation Conference, 2009.