Outreach & Short Courses : Integrated Circuit Processing

Dates

August 15-19, 2011 Cancelled

Future course dates to be announced: Register Also see: http://www.rit.edu/kgcoe/eme/icprocessing

Cost

$1675.00 - Includes tuition, text book, course material, and laboratory fee.
Note - We reserve the right to cancel courses because of low enrollment.

Objective

The objective of the course is to provide a comprehensive, hands-on educational experience in integrated circuit process engineering. Students will attend lectures that provide and overview of the fabrication of BiPolar and MOS integrated circuits. In-depth topics include statistical process control, process modeling, photolithography, and process characterization techniques. Tutorials covering topics such as device physics, computer aided design, and maskmaking are also included. The students also will participate in a structured laboratory in which a metal gate PMOS integrated circuit will be fabricated. (including design, maskmaking, processing, and testing).

Who Should Attend

This course is intended for engineers and managers seeking a better understanding of microelectronics theory and practice. The courses are ideal for a chemist, physicist, or an electrical or chemical engineer who is beginning a career in the semiconductor industry, in maskmaking, equipment or materials.

Past Participants

More than 1000 people have taken this course since 1986. They represent most U.S. semiconductor manufacturers and suppliers, as well as companies from Europe and the Pacific Rim. Researchers, scientists, engineers, equipment technicians, and marketing people with degrees ranging from AAS to Ph.D. have successfully completed this course.

Uniqueness

This course is unique because the participants actually design and fabricate a complete integrated circuit as part of the course.

Facilities

The Center for Microelectronic and Computer Engineering features more than 15,000 sq.ft. of class 10-100-1000 cleanroom. Integrated circuit and maskmaking equipment worth more than $20 million provides for state-of-the-art processing of I.C.s. This includes HP workstations with Mentor Graphic design tool, Silvaco process simulation tools, Oxidation and Diffusion Furnaces, Steppers (g-line, I-line, DUV, 193nm), Sputtering systems, Plasma Etch and IBM AS/400 Computer network for work-in-progress tracking.

Agenda

First Day

• Device Physics
• Overview of Bipolar and MOS Processes
• Lunch
• CAD of Integrated Circuits
• Computer-Aided Layout and Maskmaking Lab
• CAD Workstation
• MEBES e-Beam Maskmaking
• Microlithography

Second Day

• Oxide Growth and Diffusion
• Modelling of Oxide Growth and Diffusion
• PMOS Process Flow
• Lunch
• Oxide Growth and First Mask Lab
• Safety
• Four Point Probe Resistivity
• Diffusion Furnace Operation
• G-line 5X Stepper Operation
• Wafertrack Operation

Third Day

• Chemical Vapor Deposition
• Plasma Etching
• Advanced CMOS Processing
• Lunch
• Diffusion and Second Mask Lab
• Ellipsometry
• MOS C-V Measurements
• Analysis of Thin Films
• Facilities Overview and Tour

Fourth Day

• Metallization
• Ion Implantation
• Lunch
• Metallization and Third Mask Lab
• Sputtering of Aluminum
• Surface Analysis for Microelctronics
• In-process Chracterization
• Interference Microscopy

Fifth Day

• SUPREM Process Modelling
• Circuit Simulation
• Statistical Process Control, TQM, and Six Sigma Manufacturing
• Lunch
• Fourth Mask and Device Test Lab
• Sinter
• Wafer Probing and test
• Graduation
• Adjourn 3:00PM