Recent advancements in the field of programmable gate array technology, or programmable silicon chips, include applications where parts of a digital system can be reconfigured for on-demand customization.
A two-day training workshop about how this integrated process can be used by researchers and professors takes place March 31 and April 1 in the Kate Gleason College of Engineering at Rochester Institute of Technology.
The workshop is free and open to university faculty in engineering, computer science and information technology. Graduate students in these areas also are invited to attend. Participants will receive an introduction to the partial reconfiguration design flow, as well as learn about development steps, system capabilities and use of the reconfiguration tools.
The event is being presented by Xilinx, an international provider of the field programmable gate array technology. Parimal Patel, Xilinx senior systems engineer, will lead the training session.
“This is a chance for professors and students to learn about the new technologies and tools and incorporate them into their research and classroom activities,” says Marcin Lukowiak, assistant professor in RIT’s computer engineering department.
Participants can register for the event online.