Three dimensional Integrated circuits(3D ICs) have received much attention in recent years due to its advantages over the planar integrated circuits(ICs). Lesser Interconnect length, Integration of Heterogeneous units and lower footprint are some factors that contribute to superior performance and lower power consumption of 3D ICs. Due the stacking structure of 3D ICs, closer units gives rise to higher power densities, leading to a much higher heat dissipation. Hence, managing the temperature of the 3D ICs is a subject of utmost importance to maintain the superiority in performance and power consumption. Various floor planning and TSV placement algorithm have been put forward to manage the thermal profile of 3D ICs, during the design time. We are involved in developing the design-time framework for the thermal management of 3D ICs, which includes a novel algorithm for floor-planing and TSV placement.