Research
Biosensing Systems and Low-Power Analog
Biosensing and wearable systems need high performance from tight power and area budgets, and conventional designs pay for worst-case conditions continuously. We build adaptive analog circuits that reconfigure in response to real operating conditions, spending power only when the system demands it, and we work at the system level as well as the block level, from power delivery through signal conditioning to on-chip detection. Our work spans capacitor-less low-dropout regulators with sub-microamp quiescent current and dynamically scalable PSRR, load range, and bandwidth, extending to wirelessly powered biomedical systems where the supply carries ripple from the transfer link itself, as well as multi-modal analog front ends for biosensing. The open question we return to is how far adaptation can be pushed before the overhead of sensing conditions exceeds the power it saves.
Time-Domain Neuromorphic AI Computing
Neuromorphic hardware is limited less by network algorithms than by the cost of moving between analog and digital representations, and conventional accelerators pay that conversion cost at every layer boundary. We encode computation in signal delay rather than amplitude, which removes data converters from the compute path and keeps the arithmetic in a domain that scales with CMOS, and we work from single-device primitives up through array-level architecture. Our work spans memristor-based delay cells, clock-free dendrite circuits, architectures that sustain long chain lengths at high throughput, and the use of non-equilibrium ionic dynamics in ECRAM as a source of local short-term plasticity rather than a defect to be suppressed. The question driving this work is how much of a network's temporal behavior can be pushed into device and circuit physics, and what genuinely requires explicit architectural control.
Analog & Mixed-Signal Hardware Security
Analog and mixed-signal blocks are verified against specifications that tolerate wide process, voltage, and temperature variation, and that tolerance leaves room for structured malicious behavior that never triggers a specification failure. We study analog-native and cross-domain hardware Trojans, which exploit continuous-valued analog behavior to conceal activity beneath conventional verification, and we build and measure them in fabricated silicon rather than simulation. Our work spans attacks that embed deterministic patterns within an ADC's effective noise envelope to activate digital payloads, and payloads that modulate input-referred offset to exfiltrate data through a nominally input-only biosensor interface. Alongside the demonstrations, we are building the threat taxonomy needed to describe an attack surface that existing analog test flows were not built to examine.The harder question is detection: whether that surface can be characterized systematically, and whether defenses fit inside flows designed to find defects rather than adversaries.
Analog Design with Emerging Devices (CMOS+X)
Emerging non-volatile devices are usually evaluated as memory, and their analog behavior is treated as a non-ideality to be corrected rather than a resource to be used. We treat them as analog design primitives and ask what circuit behaviors they make available that CMOS alone does not, working from device measurement through compact modeling to circuit topology. Our work spans FeFETs, memristors, and ECRAM in analog and time-domain computing roles, measurement-calibrated compact models that let device physics inform topology and biasing directly rather than being abstracted away, and the constraint that every device we consider stays integrable with commercial CMOS processes. The standing question is whether CMOS+X analog can become a design methodology, with predictable primitives and reusable models, rather than a sequence of individual demonstrations.