- Jul 18, 2012RIT Professor Receives National Science Foundation Grant to Improve On-chip Networks with Wireless Technology
Technology being developed by researchers from three universities is expected to improve next-generation integrated circuits called network-on-chip. The work will support the growing demand for computing power and could improve overall performance of multi-core processors by integrating wireless technology with copper wiring on devices.
Amlan Ganguly, an assistant professor of computer engineering at Rochester Institute of Technology, is part of the team that received an $800,000 grant from the National Science Foundation for the project. He will be working with project leader Partha Pande, associate professor of electrical engineering at Washington State University, and researchers from Georgia Institute of Technology to develop the new infrastructure that could increase the speed and reduce the power usage in today’s computer processors, augmenting the on-chip network of miniature copper wires with wireless interconnects.
The on-chip wireless protocol that Ganguly will develop, called “Hierarchical On-Chip Millimeter-Wave Wireless Micro-Networks for Multi-Core Systems,” will allow for multiple processing engines on the chip to communicate simultaneously using a process much like that of traditional mobile telephone networks.
This first-of-its-kind process is projected to have improved results from earlier work on a token-based protocol where access on the wireless channel is granted to only a single processor one time, he says.
“The role of on-chip networks is to communicate between multiple cores, or processors, on a chip efficiently so that they can share their results and can communicate effectively with each other,” Ganguly says. “That communication has been a bottleneck over the past 10 years because the communication has been taking up a lot of energy, a lot of processing time. The major thrust in this area is to reduce that energy dissipation, to make computing systems more sustainable.”
On-chip networks are subsystems on computer chips, also referred to as integrated circuits. Currently, the chips are designed with copper wiring and circuitry. The team is developing an alternative data transfer process modeled, in part, on cellular telephone technology—with single antennae capable of accommodating multiple users at one time—yet on a significantly smaller scale on the chip.
Additionally, the new protocol is expected to reduce energy consumption for computer processors that operate day-in and day-out.
“The wireless bandwidth is very limited because it is in a small, miniature scale, so it’s not like a cellular network where you have thousands of cell phones working on really huge base stations,” Ganguly says. “When we put the wireless nodes on a chip and they try to communicate, there has to be a way that we are sure they can communicate without interfering with each other. My goal is to design a collision-free, non-interfering wireless, medium-access protocol for the network-on-chip.”
“That is a big leap in terms of usage of the available wireless resources,” Ganguly says. “You lose your dependence on energy, and that pushes us toward green computing and makes it more sustainable.”
Washington State University is overseeing the entire project and, in collaboration with RIT, is designing the architecture. Georgia Tech researchers are designing the on-chip antennae that will enable the wireless technology on the chip.Dec 13, 2011
Andrés Kwasinski, assistant professor of computer engineering at Rochester Institute of Technology, has been named to the editorial staff of two national engineering publications, Transactions on Wireless Communications and Signal Processing Magazine.
Kwasinski will serve as editor of the Institute of Electrical and Electronics Engineers’ Transactions on Wireless Communications, a peer-reviewed journal, for one year.
“Serving as editor for a technical journal offers the unique opportunity of being constantly exposed to new and exciting research work,” says Kwasinski, a member of RIT’s Kate Gleason College of Engineering since 2008. “It also carries an important responsibility, since editors manage the review process for papers and decide on their worthiness for publication.”
Effective January 2012, Kwasinski will also be area editor for IEEE’s Signal Processing Magazine, with responsibilities over seven of the magazine’s regular columns, for a three-year term. Prior to this, he was associate editor for the publication’s “In the Spotlight” column.
“Being an area editor offers the opportunity to contribute my vision applicable to the IEEE Signal Processing Society,” says Kwasinski, who adds that the magazine is considered an influential resource in the electrical and electronic engineering field.
“The position also offers the opportunity to interact regularly with the top researchers in the field of signal processing. It is a very rewarding position because it allows you to go from thinking about an idea for something interesting and valuable to be communicated to your peers, and after some hard work, to see the result in your hands, in the form of a publication that will be received and read by all your peers,” he says.
Both publications are part of the Institute of Electrical and Electronics Engineers organization, also referred to as IEEE. The international association publishes several journals, magazines, monographs and conference proceedings related to its different societies and broad engineering disciplines.
In 2009, Kwasinski published Cooperative Communications and Networking. The textbook for computer engineers was recently translated into Chinese.Oct 17, 2011
Andreas Savakis, professor of computer engineering at Rochester Institute of Technology, will take on a new role as he begins his appointment as an American Council on Education Fellow for the 2011–2012 academic year. The program offers accelerated learning experiences developed by the council to help universities advance institutional projects and personnel.
Fellows are assigned to experienced leaders at other academic institutions for mentoring and participation on host university project teams that can be mutually beneficial to both institutions. Savakis will work with University of Rochester Provost Ralph Kuncl during the fall semester on research commercialization and technology transfer for economic development. During the spring semester, he will work with Chancellor Jean MacCormack of the University of Massachusetts-Dartmouth on strategies in developing interdisciplinary Ph.D. programs.
He will also interact with RIT personnel such as the provost and academic leadership throughout the fellows program, as well as work closely with his current cohort of fellows, meeting for seminars quarterly.
“Most ACE fellows spend a semester or a full year at the host institution,” says Savakis, the first ACE Fellow from RIT, who is participating in the program after serving 10 years as department head of the computer engineering program in RIT’s Kate Gleason College of Engineering.
“The mentorship is a very important part of the process. It gives you a different perspective and an opportunity to step back and observe different aspects of a university. It is an exceptional learning experience,” he says, adding that both organizations work within common interests so that both can benefit.
Nominated by RIT Provost Jeremy Haefner, Savakis will participate in projects that can contribute to the growing research infrastructure at RIT—from advancing the corporate research and development initiatives for economic impact to preparing students for success in the global economy. He will also be able to contribute his expertise in technology transfer to host institutions.
“The ACE Fellows program, with the mentor-protégé learning experience, is the premier professional development program for individuals interested in higher education academic leadership,” says Haefner, adding that the program allows emerging leaders at a campus to learn how other institutes deal with similar issues, how leaders think and how their own skills can be sharpened to serve and lead. “It builds bridges in all sorts of ways. We are honored that Andreas was selected in the program and to be hosted by excellent mentors.”Jun 28, 2011
Students from Rochester Institute of Technology were grand-prize winners for their E-Health Intelligence System at the Freescale Technology Forum “Make It Challenge” event on June 22. The system is a health-monitoring device, small enough to fit in a patient’s pocket, and the data can be accessed anywhere in the world by physicians.
“We were very excited to win this,” says Daniel Liu, who graduated from RIT with a dual degree, Bachelor of Science/Master of Science degree in computer engineering. “We put in a lot of effort, sleeping as little as three hours each night to get this project completed in the time limit.”
The E-Health Intelligence System is a low-power mobile device that can collect different vital signs such as heart rate, respiration information or EKG data, Liu explains. It consists of a network of sensors and wireless receivers that can monitor patient vitals and transmit this information to doctors. Physicians would be able to access this medical data in real time from an Android phone or a tablet computer, improving access outside of a clinical or hospital environment.
The student design contest was sponsored by Freescale Semiconductors and held at the company’s national conference in San Antonio, June 20–23. In addition to Liu, the project team also consisted of Daniel Cheung and Sam Skalicky, students in the computer engineering program in RIT’s Kate Gleason College of Engineering. It was the first time the RIT team had entered the national contest.
Contestants were required to use at least one of Freescale’s controller hardware modules for the prototype design. Projects were judged on creativity, innovation, design efficiency and commercial suitability. The system was built using the Freescale Kinetis K60 Tower System that uses a 802.15.4 mesh networking standard in addition to a custom designed software stack, Liu explains.
For the team’s first-place finish in the Tower System category, the students received $3,000. For the grand prize overall, each member will receive a VIP weekend at a NASCAR event to view the new developments and how Freescale Semiconductor’s products are helping to improve the race car’s performance. Also included in the prize is admission to the race, pit access, grandstand seating, accommodations and monetary stipends.
The team expects to continue development, add additional functionality and present the prototype to physicians groups that have shown interest in the product.
“This grand prize recognition solidifies RIT’s position as a top engineering school,” says Ken Hsu, professor of computer engineering and the students’ project advisor. “This was a big competition. We received many compliments on the students’ design. People will know RIT has a strong engineering program, especially in embedded systems design.”
- Jun 1, 2011Department of Computer Engineering gain status of a CUDA Teaching Center for 2011-12
The Department of Computer Engineering has been named a CUDA Teaching Center for 2011-012 from Nvidia. As part of this recognition, Nvidia has donated 10 GeForce GTX480s high-performance graphics processing units and 1 Tesla C2070 GPU computing processor with 448 CUDA cores, 20 copies of the "Programming Massively Parallel Processors" book authored by David B. Kirk & Wen-mei W. Hwu, and funds to support a Teaching Assistant.
This donation will be used to develop coursework on high performance parallel computing. This recognition has been achieved thanks to the efforts of Dr. Sonia Lopez Alarcon, Assistant Professor in the department, and Dr. Roy Melton, Senior Lecturer in the department.