Amlan Ganguly Headshot

Amlan Ganguly

Associate Professor
Department of Computer Engineering
Kate Gleason College of Engineering

585-475-4082
Office Location

Amlan Ganguly

Associate Professor
Department of Computer Engineering
Kate Gleason College of Engineering

Education

B.Tech., Indian Institute of Technology (India); MS, Ph.D., Washington State University

Bio

Dr. Amlan Ganguly received his B.Tech degree from the department of Electronics and Electrical Communication Engineering at the Indian Institute of Technology, Kharagpur, India, and his M.S. and Ph.D. in Electrical and Computer Engineering from Washington State University. Dr. Ganguly’s research interests are in developing energy-efficient interconnection architectures for multicore chips using novel technologies such as wireless and photonic interconnects. He works on designing robust and failure resistant on-chip networks for future generations of multicore systems-on-chips. Dr. Ganguly is a member of the RESIST research group established at RIT to create cross-disciplinary collaborative research on Resilient, Secure and Reliable systems, networks and computation methods. He is a member of IEEE.

For more about Dr. Ganguly, see his personal webpage.

Selected publications

· Sujay Deb, Kevin Chang, Xinmin Yu, Suman Sah, Miralem Cosic, Amlan Ganguly, Partha Pande, Benjamin Belzer, Deukhyon Heo, “Design of an Energy Efficient CMOS Compatible NoC Architecture with Millimeter Wave Wireless Interconnects”, Accepted for publication in IEEE Transactions on Computers, August, 2012.

· Paul Wettin, Anuroop Vidapalapati, Amlan Ganguly and Partha Pratim Pande, “Complex Network Enabled Robust Wireless Network-on-Chip Architectures”, ACM Journal on Emerging Technologies in Computing Systems (JETC), accepted April 2012.

· Amlan Ganguly, Kevin Chang, Sujay Deb, Partha Pande, Benjamin Belzer, Christof Teuscher, “Scalable Hybrid Wireless Network-on-Chip Architectures for Multi-Core Systems”, IEEE Transactions on Computers (TC), vol. 60, issue 10, September, 2011, pp. 1485-1502.

· Amlan Ganguly, Partha Pande, Benjamin Belzer, “Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NoC Interconnects”, IEEE Transactions on VLSI (TVLSI) Vol. 17, No.11, November 2009, pp. 1626-1639.

· Pradheep Khanna Kaliraj, Patrick Sieber, Amlan Ganguly, Ipshita Datta, Debasish Datta, “Performance Evaluation of Reliability Aware Photonic Network-on-Chip Architectures”, IGCC Workshop on Lighter than Green Reliable Multicore Architectures, International Green Computing Conference (IGCC), San Jose, 2012.

· Anuroop Vidapalapati, Vineeth Vijayakumaran, Amlan Ganguly, Andres Kwasinski, “NoC Architectures with Adaptive Code Division Multiple Access based Wireless Links”, IEEE International Symposium on Circuits and Systems (ISCAS), May 20-23, Seoul, Korea.

· Amlan Ganguly, Mohsin Yusuf Ahmed, Anuroop Vidapalapati, “A Denial-of-Service Resilient Wireless NoC Architecture”, ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI), May 3-4, Salt Lake City, UT, 2012.

585-475-4082

Currently Teaching

CMPE-260
4 Credits
This course presents modern approaches to the design, modeling and testing of digital system. Topics covered are: VHDL and Verilog HDL as hardware description languages (HDLs), simulation techniques, design synthesis, verification methods, and implementation with field programmable gate arrays (FPGAs). Combinational and both the synchronous and asynchronous sequential circuits are studied. Testing and design for testability techniques are emphasized and fault tolerant and fail safe design concepts are introduced. Laboratory projects that enable students gain hands-on experience are required. The projects include complete design flow: design of the system, modeling using HDLs, simulation, synthesis and verification.
CMPE-731
3 Credits
Massive levels of integration following Moore’s Law is making modern multi-core chips all-pervasive in several domains ranging from scientific applications like weather forecasting, astronomical data analysis, bioinformatics applications to even consumer electronics. This course introduces students to current and future trends in IC Design. Students learn to identify bottlenecks in designing state-of-the-art multicore System-on-Chips (SoCs) and propose solutions to such design challenges from a cross-layer perspective spanning multiple levels of abstraction in the design process. Low-power and high-speed testing of multicore chips is an important design issue in Design for Testability (DFT) of such massive multicore systems. In this course students learn various issues and solutions to ongoing challenges in SoC testing. The instruction will rely on lectures, textbooks, seminal and cutting edge publication articles and term projects. Students will be evaluated based on homework assignments, class presentations, examinations and projects.
CMPE-630
3 Credits
This course will cover the basic theory and techniques of Digital Integrated Circuit Design in CMOS technology. Topics include CMOS transistor theory and operation, design and implementation of CMOS circuits, fabrication process, layout and physical design, delay and power models, static and dynamic logic families, testing and verification, memory and nanoscale technologies. Laboratory assignments and project facilitate in hands-on learning of circuit-level design and simulation, layout and parasitic extractions, pre and post-layout verification and validation, full-custom flow and Synthesis based flow, using industry standard CAD tools.
CMPE-530
3 Credits
This course will cover the basic theory and techniques of Digital Integrated Circuit Design in CMOS technology. Topics include CMOS transistor theory and operation, design and implementation of CMOS circuits, fabrication process, layout and physical design, delay and power models, static and dynamic logic families, testing and verification, memory and nanoscale technologies. Laboratory assignments and project facilitate in hands-on learning of circuit-level design and simulation, layout and parasitic extractions, pre and post-layout verification and validation, full-custom flow and Synthesis based flow, using industry standard CAD tools.
ENGT-510
0 Credits
This faculty directed undergraduate research experience involves student(s) in a research project. Under the guidance of CET faculty and using one or a variety of methods, students will collect data and contribute to problem solving within a research environment. As an undergraduate research experience, emphasis is on the process of scientific research, including problem definition, formulating a research plan, data collection/analysis and interpretation based on existing research. Department permission is required.
CMPE-792
1 - 3 Credits
Graduate Project is a scholarly undertaking that addresses an immediate and practical problem with tangible outcomes. A formal report, presentation, or demonstration is required. The student must obtain the approval of an appropriate faculty adviser to guide the project before registering.
CMPE-499
0 Credits
After completing Co-op Seminar (EGEN-099) or Co-op Workshop as well as meeting Co-op enrollment requirements, Computer Engineering students should register for CMPE-499 for each term of full-time, paid employment in the Computer Engineering field. Students who take on Spring-Summer or Summer-Fall Co-ops must register for both the semester term and the summer term. Students must obtain permission from the Computer Engineering office for any exception to the assigned Co-op blocks.
CMPE-599
1 - 4 Credits
Allows upper-level undergraduate students an opportunity to independently investigate, under faculty supervision, aspects of the field of computer engineering that are not sufficiently covered in existing courses. Proposals for independent study activities must be approved by both the faculty member supervising the independent study and the department head.
CMPE-699
0 Credits
Graduate co-op aims to enhance the educational experience of graduate students through full-time paid employment during an academic quarter at positions in the Computer Engineering field. Registration is optional and is recommended for summer term only after the completion of all course work.
CMPE-790
1 - 9 Credits
Thesis research investigates an independent problem to demonstrate professional maturity. A formal written thesis and an oral defense are required. The student must obtain the approval of an appropriate faculty adviser to guide the thesis before registering.
CMPE-799
1 - 3 Credits
Allows graduate students an opportunity to independently investigate, under faculty supervision, aspects of the field of computer engineering that are not sufficiently covered in existing courses. Proposals for independent study activities are subject to approval by both the faculty member supervising the independent study and the department head.

Select Scholarship

Published Conference Proceedings
Relyea, R., et al. "Multimodal localization for autonomous agents." Proceedings of the Proceedings of Electronic Imaging: Image Processing Algorithi. Ed. IEEE. San Francisco, CA: n.p., 2019. Web.
Li, M., et al. "Simulation and Analysis of a Deep Reinforcement Learning Approach for Task Selection by Autonomous Material Handling Vehicles." Proceedings of the Proceedings of the 2018 Winter Simulation Conference. Ed. IEEE. Piscataway, NJ: n.p., Web.
Ahmed, M. M., et al. "A One-to-many Traffic Aware Wireless Network-in-Package for Multi-Chip Computing Platorms." Proceedings of the Proceedings of IEEE System-On-Chip Conference (SoCC). Ed. IEEE. Arlington, VA: n.p., 2018. Web.
Ahmed, M. M., N. Mansoor, and A. Ganguly. "An Asymmetric, Energy Efficient One-to-Many Traffic-Aware Wireless Network-in-Package Interconnection Architecture for Multichip Systems." Proceedings of the Proceedings of International Green and Sustainable Computing Conference (IGSC). Ed. IEEE. Pittsburgh, PA: n.p., 2018. Web.
Vashist, A., A. Ganguly, and M. Indovina. "Testing WiNoC-Enabled Multicore Chips with BIST for Wireless Interconnects." Proceedings of the 2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS). Ed. IEEE. Turin, Italy: n.p., 2018. Web.
Shinde, T., et al. "A 0.24pJ/bit, 16 Gbps OOK Transmitter Circuit in 45-nm CMOS for Inter and Intra-Chip Wireless Interconnects." Proceedings of the Proceedings of the 2018 on Great Lakes Symposium on VLSI (GLSVLSI '18). Ed. IEEE. New York, NY: n.p., 2018. Web.
Narde, R. S., J. Venkataraman, and A. Ganguly. "Emhancement of Intra-chip Transmission between Wireless Interconnects using Artificial Magnetic Conductors." Proceedings of the 2018 IEEE International Symposium on Antennas and Propagation & USNC/URSI National Radio Science Meeting. Ed. IEEE. Boston, MA: n.p., 2018. Web.
Narde, R. S., et al. "On-Chip Antennas for Inter-Chip Wireless Interconnections: Challenges and Opportunities." Proceedings of the 12th European Conference on Antennas and Propagation (EuCAP). Ed. IEEE. London, UK: n.p., 2018. Web.
Narde, R.S., et al. "On-Chip Antennas for Inter-Chip Wireless Interconnections: Challenges and Opportunities." Proceedings of the 12th European Conference on Antennas and Propagation (EuCAP). Ed. EuCAP. London, UK: EuCAP, 2018. Print.
Ahmed, M.M., et al. "Increasing Interposer Utilization: A Scalable, Energy Efficient and High Bandwidth Multicore-Multichip Integration Solution." Proceedings of the IEEE Green and Sustainable Computing Conference (IGSC). Ed. IEEE. Orlando, FL: IEEE, 2017. Print.
Dharb, G., et al. "PaSE: A Parallel Speedup Estimation Framework for Network-On-Chip Based Multicore Systems." Proceedings of the IEEE IGSC Workshop on Sustainability in Multi/Manycore Systems. Ed. IEEE. Orlando, FL: IEEE, 2017. Print.
Saxena, S., et al. "Energy-Efficiency in Interconnection Fabrics for Inter and Intra-Chip Communication Using Graphene-Based THz-Band Antennas." Proceedings of the IEEE IGSC Workshop on Sustainability in Multi/Manycore Systems. Ed. IEEE. Orlando, FL: IEEE, 2017. Print.
Umamaheswaran, S.G., et al. "Reducing Power Consumption of Datacenter Networks with 60GHz Wireless Server-to-Server Links." Proceedings of the IEEE GLOBECOM. Ed. IEEE. Marina Bay Sands, Singapore: IEEE, 2017. Web.
Shamim, M.S., et al. "Energy-Efficient Wireless Interconnection Framework for Multichip Systems with In-Package Memory Stacks." Proceedings of the IEEE System-on-Chip Conference (SOCC). Ed. IEEE. Munich, Germany: IEEE, 2017. Print.
Ganguly, A., et al. "A 0.36pJ/bit, 17Gbps OOK Receiver in 45-nm CMOS for Inter and Intra-Chip Wireless Interconnects." Proceedings of the IEEE System-on-Chip Conference (SOCC). Ed. IEEE. Munich, Germany: IEEE, 2017. Print.
Mamun, S.A., et al. "An Energy-Efficient, Wireless Top-of-Rack to Top-of-Rack Datacenter Network Using 60GHz Links." Proceedings of the IEEE International Conference on Green Computing and Communication (GreenCom). Ed. IEEE. Exeter, UK: IEEE, 2017. Print.
Narde, R.S., J. Venkataraman, and A. Ganguly. "Feasibility Study of Transmission Between Wireless Interconnects in Multichip Multicore Systems." Proceedings of the IEEE International Symposium on Antennas and Propagation & USNC/URSI National Radio Science Meeting (APS). Ed. IEEE. San Diego, CA: IEEE, 2017. Print.
Munuswamy, C.K., J. Venkataraman, and A. Ganguly. "Design of Antennas for 3D Wireless Network-On-Chip with Micro-Fluidic Cooling Layers." Proceedings of the IEEE International Symposium on Antennas and Propagation (APSURSI). Ed. IEEE. Fajardo, Puerto Rico: IEEE, 2016. Print.
Mansoor, Naseef, Md Shahriar Shamim, and Amlan Ganguly. "A Demand-Aware Predictive Dynamic Bandwidth Allocation Mechanism for Wireless Network-On-Chip." Proceedings of the ACM Workshop on System Level Interconnect Prediction (SLIP). Ed. IEEE. Austin, TX: IEEE, 2016. Print.
Shamim, Md Shahriar, et al. "Co-Design of 3D Wireless Network-On-Chip Architectures with Microchannel-Based Cooling." Proceedings of the IEEE/ACM International Green and Sustainable Computing Conference. Ed. IEEE/ACM. Las Vegas, NV: IEEE/ACM, 2015. Print.
Shamim, M.S., et al. "Temperature-aware Wireless Network-on-Chip Architecture." Proceedings of the IEEE/ACM International Green Computing Conference (IGCC). Ed. Ali Hurson. Dallas, TX: IEEE/ACM, 2014. Web.
Shamim, Md Shahriar, et al. "Energy-efficient Wireless Network-on-chip Architecture with Log-periodic On-chip Antennas." Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI. Ed. Joseph Cavallaro and Tong Zhang. Houston, TX: IEEE, 2014. Web.
Shah, Ankit, et al. "Heterogeneous Photonic Network-on-Chip with Dynamic Bandwidth Allocation." Proceedings of the System-on-Chip Conference (SOCC), 2014 27th IEEE International. Ed. Kaijian Shi. Las Vegas, NV: IEEE, 2014. Web.
Mansoor, Naseef, Manoj Yuvaraj, and Amlan Ganguly. "A Robust Medium Access Mechanism for Millimeter-Wave Wireless Network-on-Chip Architecture." Proceedings of the IEEE System on Chip Conference (SOCC), Sept 2013, Germany. Ed. Norbert Schuhmann, Fraunhofer IIS. Erlangen, Germany: IEEE, Web.
Mansoor, Naseef, Amlan Ganguly, and Manoj Yuvaraj. "An Energy-efficient and Robust Millimeter-wave Wireless Network-on-Chip Architecture." Proceedings of the IEEE International Symposium on Design and Fault Tolerance in VLSI and Nanotechnology Systems, 2013, New York. Ed. Sandip Kundu (University of Massachusetts, Amherst, USA). New York, NY: IEEE, Web.
Wettin, Paul, et al. "Energy-Efficient Multicore Chip Design Through Cross-Layer Approach." Proceedings of the Design, Automation and Test in Europe (DATE), Europe, 2013. Ed. Enrico Macii, Politecnico di Torino, IT. Grenoble, France, FR: IEEE, 2013. Web.
Wettin, Paul, et al. "Design Space Exploration for Reliable mm-Wave Wireless NoC Architectures." Proceedings of the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2013, Ashburn, VA. Ed. TarekEl-Ghazawi, George Washington University. Ashbrun, VA: IEEE, 2013. Web.
Murray, Jacob, et al. "Evaluating Effects of Thermal Management in Wireless NoC-Enabled Multicore Architectures." Proceedings of the IEEE International Green Computing Conference (IGCC), 2013, Arlington, VA. Ed. Ishfaq Ahmed, Behrooz Shirazi. Arlington, VA: IEEE, 2013. Web.
Wettin, Paul, et al. "Energy-Efficient Multicore Chip Design Through Cross-Layer Approach." Proceedings of the Design, Automation and Test in Europe. Ed. IEEE. Grenoble, France: IEEE, 2013. Print.
Kaliraj, Pradheep Khanna, et al. "Performance Evaluation of Reliability Aware Photonic Network-on-Chip Architectures." Proceedings of the IGCC Workshop on Lighter than Green Reliable Multicore Architectures, International Green Computing Conference (IGCC). Ed. IGCC. San Jose, CA: IGCC, 2012. Print.
Vidapalapati, Anuroop, et al. "NoC Architectures with Adaptive Code Division Multiple Access Based Wireless Links." Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS). Ed. IEEE. Seoul, Korea: IEEE, 2012. Print.
Ganguly, Amlan, Mohsin Yusuf Ahmed, and Anuroop Vidapalapati. "A Denial-of-Service Resilient Wireless NoC Architecture." Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI). Ed. ACM. Salt Lake City, UT: ACM, 2012. Print.
Ganguly, Amlan, et al. "A Unified Error Control Coding Scheme to Enhance the Reliability of a Hybrid Wireless Network-on-Chip." Proceedings of the IEEE Defect and Fault Tolerance Symposium (DFTS). Ed. unknown. Vancouver, Canada: IEEE, 2011. Print.
Ganguly, Amlan, Paul Wettin, and Partha Pande. "Complex Network Inspired Fault-tolerant NoC Architectures with Wireless Links." Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS). Ed. unknown. Pittsburgh, PA: IEEE/ACM, 2011. Print.
Ganguly, Amlan, Partha Kundu, and Pradip Bose. "Curbing Energy Cravings in Networks: A Cross-sectional View Across the Micro-Macro Boundary." Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS). Ed. unknown. Pittsburgh, PA: IEEE/ACM, 2011. Print.
Pande, Partha, et al. "Sustainability through Massively Integrated Computing: Are We Ready to Break the Energy Efficiency Wall for Single-Chip Platforms?" Proceedings of the Design, Automation and Test in Europe. Ed. unknown. France: IEEE/ACM, 2011. Print.
Journal Paper
Ganguly, A., et al. "The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems." MDPI Journal of Low Power Electronics and Applications 8. 5 (2018): 1-36. Web.
Mamun, S. A., et al. "Performance Evaluation of a Power-Efficient and Robust 60GHz Wireless Server-to-Server Datacenter Network." IEEE Transactions on Green Communications and Networking 2. 4 (2018): 1174-1185. Web.
Shamim, M.S., et al. "A Wireless Interconnection Framework for Seamless Inter and Intra-Chip Communication in Multichip Systems." IEEE Transactions on Computers 66. 3 (2017): 389-402. Web.
Mondal, H.K., et al. "Interference-Aware Wireless Network-On-Chip Architecture Using Directional Antennas." IEEE Transactions on Multi-Scale Computing Systems 3. 3 (2017): 193-205. Web.
Ganguly, Amlan, Partha Pande, and Benjamin Belzer. "Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NoC Interconnects." IEEE Transactions on VLSI (TVLSI) 17. 11 (2009): 1626-1639. Print.
Ganguly, Amlan, et al. "Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding." Journal of Electronic Testing: Theory and Applications (JETTA). Special Issue on Defect and Fault Tolerance (2008): 67-81. Print.
Pande, Partha, et al. "Energy Reduction Through Crosstalk Avoidance Coding in Networks on Chip." Journal of System Architecture (JSA) 54. 3-4 (2008): 441-451. Print.
Mansoor, Naseef, Pratheep Iruthayaraj, and Amalan Ganguly. "Design Methodology for a Robust and Energy-Efficient Millimeter-Wave Wireless Network-On-Chip." IEEE Transactions on Multi-Scale Computing Systems 1. 1 (2015): 33-45. Print.
Vijayakumaran, Vineeth, et al. "CDMA Enabled Wireless Network-on-Chip." ACM Journal on Emerging Technologies in Computing Systems (JETC) 10. 4 (2014): 28-53. Print.
Wettin, Paul, et al. "Design Space Exploration for Wireless NoCs Incorporating Irregular Network Routing." Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 33. 11 (2014): 1732-1745. Print.
Vijayakumaran, Vineeth, et al. "CDMA Enabled NoC Architectures with Wireless Interconnects." ACM Journal of Emerging Technologies in Computing (JETC) 10. 4 (2014): 636-639. Print.
Deb, Sujay, et al. "Design of an Energy Efficient CMOS Compatible NoC Architecture with Millimeter-Wave Wireless Interconnects." IEEE Transactions on Computers 62. 12 (2013): 2382- 2396. Print.
Deb, Sujay, et al. "Design of an Energy Efficient CMOS Compatible NoC Architecture with Millimeter Wave Wireless Interconnects." IEEE Transactions on Computers. (2012): 2382-2396. Print.
Wettin, Paul, et al. "Complex Network Enabled Robust Wireless Network-on-Chip Architectures." ACM Journal on Emerging Technologies in Computing Systems (JETC). (2012): -. Print.
Deb, Sujay, et al. "Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges." IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) 2. 2 (2012): 228-239. Print.
Ganguly, Amlan, et al. "Scalable Hybrid Wireless Network-on-Chip Architectures for Multi-Core Systems." IEEE Transactions on Computers 60. 10 (2011): 1485-1502. Print.
Chang, Kevin, et al. "Performance Evaluation and Design Trade-Offs for Wireless Network-on-Chip Architectures." ACM Journal on Emerging Technologies in Computing Systems. (2011): 000-000. Print.
Invited Keynote/Presentation
Ganguly, Amlan. "Enabling On-Chip Wireless Interconnects: Robustness in Wireless Network-on-Chip Architectures." System Level Interconnection Prediction (SLIP), Colocated with Design Automation and Conference (DAC). IEEE. Austin, TX. 2 Jun. 2013. Lecture.
Ganguly, Amlan. "Answer from Nature: Addressing the Challenges of Fault-Tolerance and Integration of Emerging On-Chip Interconnects in NoCs." Diagnostic Services in Networks-on-Chips. Design and Automation Conference. San Diego, San Diego, CA. 5 Jun. 2011. Lecture.
Full Length Book
Pande, Partha, Amlan Ganguly, and Krishnendu Chakrabarty. Design Technologies for Green and Sustainable Computing Systems. 1 ed. Chambersburg, PA: Springer, 2013. Print.
Book Chapter
Pande, Partha, et al. "Energy-Efficient Network-on-Chip Architectures for Multicore Systems." Handbook of Energy-Aware and Green Computing. Ed. Ishfaq Ahmad and Sanjay Ranka. USA: Hapman and Hall/CRC Press Taylor and Francis Group LLC, 2011. 000-000. Print.