Dorin Patru Headshot

Dorin Patru

Associate Professor
Department of Electrical and Microelectronic Engineering
Kate Gleason College of Engineering

585-475-2388
Office Location
Office Mailing Address
9-3051

Dorin Patru

Associate Professor
Department of Electrical and Microelectronic Engineering
Kate Gleason College of Engineering

Education

BS, MS, Technical University of Cluj-Napoca (Romania); Ph.D., Washington State University

Bio

Professor Dorin Patru teaches digital and computer, circuits and systems courses. He joined the department in fall 2002. He received a B.S. and M.S. in Electrical Engineering from the Technical University of Cluj-Napoca, Romania, and a Ph.D. in Electrical Engineering from Washington State University.

Dr. Patru, his colleagues, and his research assistants are currently pursuing both applied and basic research. An ongoing project, sponsored by Hewlett-Packard, investigates the tradeoffs in implementing image-processing systems in ASICs (Application Specific Integrated Circuit) and FPGAs Field Programmable Gate Array), with a focus on overlapping reconfiguration with processing. A second project sponsored by HP examines the tradeoffs in performing parallel image processing in software using SIMD Single Instruction Multiple Data) instruction set extensions. A third project explores the potential of a computer architecture for late and post silicon technologies, which is tolerant to device and component failures, while at the same time allowing for massive parallel and concurrent computing. A forth and most recent project focuses on the development of a high spatial- and temporal- resolution mobile eye tracking system to support an ongoing NSF project.

For more about Dr. Patru, see his website.

Selected recent publications:

· Ryan Toukatly, Dorin Patru, Eli Saber, Eric Peskin, Gene Roylance, Brad Larson, “Performance Analysis of a Color Space Conversion Engine Implemented Using Dynamic Partial Reconfiguration”, IS&T and SPIE Conference, San Francisco, CA, 2013.

· Eric Welch, Dorin Patru, Eli Saber, Kurt Bengtson, “A Study of the Use of SIMD Instructions for Two Image Processing Algorithms”, IEEE 2012 Western New York Image Processing Workshop, Rochester, NY, 2012.

· Alexander Mykyta, Dorin Patru, Eli Saber, Gene Roylance, Brad Larson, "Reconfigurable Framework for High-Bandwidth Stream-Oriented Data Processing", Proceedings of the IEEE SoCC Conference, Niagara Falls, NY, 2012.

· Dorin Patru and Scott R. Hudson, "Optically Injected Logic Circuits for Remote Powered Systems on a Chip", Elsevier Journal of Computers and Electrical Engineering, 2010.

585-475-2388

Currently Teaching

EEEE-220
3 Credits
In the first part, the course covers the design of digital systems using a hardware description language. In the second part, it covers the design of large digital systems using the computer design methodology, and culminates with the design of a reduced instruction set central processing unit, associated memory and input/output peripherals. The course focuses on the design, capture, simulation, and verification of major hardware components such as: the datapath, the control unit, the central processing unit, the system memory, and the I/O modules. The lab sessions enforce and complement the concepts and design principles exposed in the lecture through the use of CAD tools and emulation in a commercial FPGA. This course assumes a background in C programming.
EEEE-499
0 Credits
One semester of paid work experience in electrical engineering.
EEEE-621
3 Credits
The purpose of this course is to expose students to the design of single and multicore computer systems. The lectures cover the design principles of instructions set architectures, non-pipelined data paths, control unit, pipelined data paths, hierarchical memory (cache), and multicore processors. The design constraints and the interdependencies of computer systems building blocks are being presented. The operation of single core, multicore, vector, VLIW, and EPIC processors is explained. In the first half of the semester, the lab projects enforce the material presented in the lectures through the design and physical emulation of a pipelined, single core processor. This is then being used in the second half of the semester to create a multicore computer system. The importance of hardware/software co-design is emphasized throughout the course. Students are further required to choose a research topic in the area of computer systems, perform bibliographic research, and write a research paper following a prescribed format.
EEEE-521
3 Credits
The purpose of this course is to expose students to the design of single and multicore computer systems. The lectures cover the design principles of instructions set architectures, non-pipelined data paths, control unit, pipelined data paths, hierarchical memory (cache), and multicore processors. The design constraints and the interdependencies of computer systems building blocks are being presented. The operation of single core, multicore, vector, VLIW, and EPIC processors is explained. In the first half of the semester, the lab projects enforce the material presented in the lectures through the design and physical emulation of a pipelined, single core processor. This is then being used in the second half of the semester to create a multicore computer system. The importance of hardware & software co-design is emphasized throughout the course.
EEEE-721
3 Credits
In this course the student is introduced to advanced topics in computer systems design. It is expected that the student is already familiar with the design of a non-pipelined, single core processor. The lectures cover instruction level parallelism, limits of the former, thread level parallelism, multicore processors, optimized hierarchical memory design, storage systems, and large-scale multiprocessors for scientific applications. The projects reinforce the lectures material, by offering a hands-on development and system level simulation experience.

Select Scholarship

Published Conference Proceedings
Mazza, James, et al. "A Comparison of Hardware/Software Techniques in the Speedup of Color Image Processing Algorithms." Proceedings of the IEEE Western NY Image Processing Workshop. Ed. IEEE. Rochester, NY: IEEE, 2014. Web.
Whitesell, Jamison, et al. "Design for Implementation of Color Image Processing Algorithms." Proceedings of the SPIE 2014. Ed. SPIE. San Francisco, CA: SPIE, 2014. Print.
Larson, Ryan Toukatly, Dorin Patru, Eli Saber, Eric Peskin, Gene Roylance, Brad. "Analysis of a Color Space Conversion Engine Implemented Using Dynamic Partial Reconfiguration." Proceedings of the Electronic Imaging 2013. Ed. SPIE/IS&T. San Francisco, CA: SPIE/IS&T, 2013. Print.
Mykyta, Alexander, et al. "Reconfigurable Framework for High-Bandwidth Stream-Oriented Data Processing." Proceedings of the IEEE SoCC Conference, Niagara Falls, NY 2012. Ed. IEEE. Niagara Falls, NY: n.p., Print.
Welch, Eric, et al. "A Study of the Use of Simd Instructions for Two Image Processing Algorithms." Proceedings of the IEEE WNYIPW 2012, Rochester, NY 2012. Ed. IEEE. Rochester, NY: IEEE, Print.
Published Article
Patru, Dorin, and R. Scott Hudson. “Optically injected logic circuits for remote-powered systems on a chip.” Computers & Electrical Engineering,36.6 (2010): 1075-1092. Print. ≠ *