Dorin Patru Headshot

Dorin Patru

Associate Professor

Department of Electrical and Microelectronic Engineering
Kate Gleason College of Engineering
dxpeee@rit.edu
585-475-2388
Office Location
GLE-3051
Office Mailing Address
9-3051

Dorin Patru

Associate Professor

Department of Electrical and Microelectronic Engineering
Kate Gleason College of Engineering

Education

BS, MS, Technical University of Cluj-Napoca (Romania); Ph.D., Washington State University

Bio

Professor Dorin Patru teaches digital and computer, circuits and systems courses. He joined the department in fall 2002. He received a B.S. and M.S. in Electrical Engineering from the Technical University of Cluj-Napoca, Romania, and a Ph.D. in Electrical Engineering from Washington State University.

Dr. Patru, his colleagues, and his research assistants are currently pursuing both applied and basic research in the areas of custom digital systems and digital computer systems. The applied research focuses on aerospace systems (cryogenic image sensors and cubesats), and automated test equipment for photonic integrated circuits. The basic research focuses on novel and efficient digital data processing architectures.

For more information about Dr. Patru, please visit his professional website.

Selected recent publications:

· Ryan Toukatly, Dorin Patru, Eli Saber, Eric Peskin, Gene Roylance, Brad Larson, “Performance Analysis of a Color Space Conversion Engine Implemented Using Dynamic Partial Reconfiguration”, IS&T and SPIE Conference, San Francisco, CA, 2013.

· Eric Welch, Dorin Patru, Eli Saber, Kurt Bengtson, “A Study of the Use of SIMD Instructions for Two Image Processing Algorithms”, IEEE 2012 Western New York Image Processing Workshop, Rochester, NY, 2012.

· Alexander Mykyta, Dorin Patru, Eli Saber, Gene Roylance, Brad Larson, 'Reconfigurable Framework for High-Bandwidth Stream-Oriented Data Processing', Proceedings of the IEEE SoCC Conference, Niagara Falls, NY, 2012.

· Dorin Patru and Scott R. Hudson, 'Optically Injected Logic Circuits for Remote Powered Systems on a Chip', Elsevier Journal of Computers and Electrical Engineering, 2010.

dxpeee@rit.edu
585-475-2388
Personal Links
Personal Website

Select Scholarship

Published Conference Proceedings
Prechtl, Ian, et al. "“CLAM: Compiler Lease of Cache Memory”." Proceedings of the ACM Memory Systems Conference Proceedings, MEMSYS October 2020. Ed. ACM. Washington, DC, USA: ACM, 2020. Web.
Ding, Chen, Dong Chen, and Dorin Patru. "“CLAM: Compiler Leasing of Accelerator Memory”." Proceedings of the 32nd Workshop on Languages and Compilers for Parallel Computing (LCPC) at Georgia Tech, Atlanta, GA, October 2019. Ed. Georgia Tech. Atlanta, GA, USA: Georgia Tech, 2019. Web.
Nguyen, Chi H. and et al. "Integration and instrument characterization of the cosmic infrared background experiment 2 (CIBER-2)"." Proceedings of the Proc. SPIE 10698, Space Telescopes and Instrumentation 2018: Optical, Infrared, and Millimeter Wave, 106984J (6 July 2018). Ed. SPIE. USA, USA: n.p., 2018. Web.
Park, Won-Kee and et al. "Development of data storage system and GSE for cosmic infrared background experiment 2 (CIBER-2)"." Proceedings of the Proc. SPIE 10698, Space Telescopes and Instrumentation 2018: Optical, Infrared, and Millimeter Wave, 1069849 (6 July 2018). Ed. SPIE. USA, USA: SPIE, 2018. Web.
Herdzik, David and et al. "“SOAP – Sea Of Atomic Processors”." Proceedings of the Energy-efficient Networks of Computers: from the Chip to the Cloud (E2NC) Workshop, 6th IEEE International Green and Sustainable Computing Conference, 2015. Ed. IEEE. Las Vegas, NV, USA: n.p., 2015. Web.
Barbosu, M. and D. Patru. "“Autonomous Small Spacecraft Missions”." Proceedings of the Proceedings of the Autonomous Spacecraft Navigation. Ed. WE-Heraeus Seminar. Germany, Germany: n.p., 2015. Web.
Mazza, James, et al. "A Comparison of Hardware/Software Techniques in the Speedup of Color Image Processing Algorithms." Proceedings of the IEEE Western NY Image Processing Workshop. Ed. IEEE. Rochester, NY: IEEE, 2014. Web.
Whitesell, Jamison, et al. "Design for Implementation of Color Image Processing Algorithms." Proceedings of the SPIE 2014. Ed. SPIE. San Francisco, CA: SPIE, 2014. Print.
Larson, Ryan Toukatly, Dorin Patru, Eli Saber, Eric Peskin, Gene Roylance, Brad. "Analysis of a Color Space Conversion Engine Implemented Using Dynamic Partial Reconfiguration." Proceedings of the Electronic Imaging 2013. Ed. SPIE/IS&T. San Francisco, CA: SPIE/IS&T, 2013. Print.
Mykyta, Alexander, et al. "Reconfigurable Framework for High-Bandwidth Stream-Oriented Data Processing." Proceedings of the IEEE SoCC Conference, Niagara Falls, NY 2012. Ed. IEEE. Niagara Falls, NY: n.p., Print.
Welch, Eric, et al. "A Study of the Use of Simd Instructions for Two Image Processing Algorithms." Proceedings of the IEEE WNYIPW 2012, Rochester, NY 2012. Ed. IEEE. Rochester, NY: IEEE, Print.
Peer Reviewed/Juried Poster Presentation or Conference Paper
Loewenthal, Jared and et al. "A 3U Cubesat Platform for Plant Growth Experiments"." Proceedings of the Proceedings of the AIAA/USU Conference on Small Satellites 2019. Ed. AIAA/USU. Logan, UT, USA: AIAA/USU.
Patru, Dorin and Mihail Barbosu. "“COARSSS – Chain of Autonomous Remote Sensing Small Spacecraft”." Proceedings of the Proceedings of the AIAA/USU Conference on Small Satellites 2017. Ed. AIAA/USU. Logan, UT, USA: AIAA/USU.
Published Article
Patru, Dorin, and R. Scott Hudson. “Optically injected logic circuits for remote-powered systems on a chip.” Computers & Electrical Engineering,36.6 (2010): 1075-1092. Print. É  *

Currently Teaching

EEEE-220
Digital Systems II
3 Credits
In the first part, the course covers the design of digital systems using a hardware description language. In the second part, it covers the design of large digital systems using the computer design methodology, and culminates with the design of a reduced instruction set central processing unit, associated memory and input/output peripherals. The course focuses on the design, capture, simulation, and verification of major hardware components such as: the datapath, the control unit, the central processing unit, the system memory, and the I/O modules. The lab sessions enforce and complement the concepts and design principles exposed in the lecture through the use of CAD tools and emulation in a commercial FPGA. This course assumes a background in C programming.
EEEE-499
Co-op
0 Credits
One semester of paid work experience in electrical engineering.
EEEE-521
Design of Computer Systems
3 Credits
The purpose of this course is to expose students to the design of single and multicore computer systems. The lectures cover the design principles of instructions set architectures, non-pipelined data paths, control unit, pipelined data paths, hierarchical memory (cache), and multicore processors. The design constraints and the interdependencies of computer systems building blocks are being presented. The operation of single core, multicore, vector, VLIW, and EPIC processors is explained. In the first half of the semester, the lab projects enforce the material presented in the lectures through the design and physical emulation of a pipelined, single core processor. This is then being used in the second half of the semester to create a multicore computer system. The importance of hardware & software co-design is emphasized throughout the course.
EEEE-621
Design of Computer Systems
3 Credits
The purpose of this course is to expose students to the design of single and multicore computer systems. The lectures cover the design principles of instructions set architectures, non-pipelined data paths, control unit, pipelined data paths, hierarchical memory (cache), and multicore processors. The design constraints and the interdependencies of computer systems building blocks are being presented. The operation of single core, multicore, vector, VLIW, and EPIC processors is explained. In the first half of the semester, the lab projects enforce the material presented in the lectures through the design and physical emulation of a pipelined, single core processor. This is then being used in the second half of the semester to create a multicore computer system. The importance of hardware/software co-design is emphasized throughout the course. Students are further required to choose a research topic in the area of computer systems, perform bibliographic research, and write a research paper following a prescribed format.
EEEE-721
Advanced Topics in Computer System Design
3 Credits
In this course the student is introduced to advanced topics in computer systems design. It is expected that the student is already familiar with the design of a non-pipelined, single core processor. The lectures cover instruction level parallelism, limits of the former, thread level parallelism, multicore processors, optimized hierarchical memory design, storage systems, and large-scale multiprocessors for scientific applications. The projects reinforce the lectures material, by offering a hands-on development and system level simulation experience.

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