Jinming Zhuang
Assistant Professor, Computer Engineering
Jinming Zhuang
Assistant Professor, Computer Engineering
Bio
Dr. Jinming Zhuang is a tenure-track Assistant Professor in the Department of Computer Engineering at the Rochester Institute of Technology. He received his B.E. in Electronic Engineering from the University of Electronic Science and Technology of China (UESTC) in 2021 and completed his Ph.D. in the School of Engineering at Brown University in 2026. His research interests lie in Heterogeneous Computing with NPUs, GPUs, and FPGAs for AI, as well as Compiler Optimization & Programming Abstraction for hardware. He has published 17 papers in IEEE/ACM computer architecture and design automation conferences and journals, including FPGA, DAC, SC, RTSS, ICCAD, TCAD, TRETS, etc. His work has received the 2025 ACM/SIGDA FPGA Best Paper Nominee, the 2024 IEEE IGSC Best Viewpoint Paper, and the 2021 ACM/IEEE DAC Young Student Fellow Best Video Award.
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[TRETS’26] Erwei Wang, Samuel Bayliss, Andra Bisca, Zachary Blair, Sangeeta Chowdhary, Kristof Denolf, Jeff Fifield, Brandon Freiberger, Erika Hunhoff, Phil James-Roxby, Jack Lo, Joseph Melber, Stephen Neuendorffer, Eddie Richter, André Rosti, Javier Setoain, Gagandeep Singh, Endri Taka, Pranathi Vasireddy, Zhewen Yu, Niansong Zhang, and Jinming Zhuang. 2026. “From Loop Nests to Silicon: Mapping AI Workloads onto AMD NPUs with MLIR-AIR”. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2026. Open-source: https://github.com/Xilinx/mlir-air.
[FPGA’25] Jinming Zhuang*, Shaojie Xiang*, Hongzheng Chen, Niansong Zhang, Zhuoping Yang, Tony Mao, Zhiru Zhang, Peipei Zhou, “ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines,” In Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), 2025. (FPGA’25 Best Paper Nominee). Open source: https://github.com/arc-research-lab/Aries.
[TCAD’24] Peiyan Dong*, Jinming Zhuang*, Zhuoping Yang, Shixin Ji, Dongkuan Xu, Yanyu Li, Heng Huang, Jingtong Hu, Alex K. Jones, Yiyu Shi, Yanzhi Wang, Peipei Zhou, “EQ-ViT: Algorithm-Hardware Co-Design for End-to-End Acceleration of Real-Time Vision Transformer Inference on Versal ACAP Architecture,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), 2024.
[TRETS’24] Jinming Zhuang, Jason Lau, Hanchen Ye, Zhuoping Yang, Shixin Ji, Jack Lo, Kristof Denolf, Stephen Neuendorffer, Alex Jones, Jingtong Hu, Yiyu Shi, Deming Chen, Jason Cong, Peipei Zhou, “CHARM 2.0: Composing Heterogeneous Accelerators for Deep Learning on Versal ACAP Architecture,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2024.
[FPGA’24] Jinming Zhuang, Zhuoping Yang, Shixin Ji, Heng Huang, Alex K. Jones, Jingtong Hu, Yiyu Shi, Peipei Zhou, “SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff Design Space Exploration,” In Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), 2024. Open-source: https://github.com/arc-research-lab/SSR.
[DAC’23] Jinming Zhuang, Zhuoping Yang, Peipei Zhou, “High Performance, Low Power Matrix Multiply Design on ACAP: from Architecture, Design Challenges, and DSE Perspectives,” 60th ACM/IEEE Design Automation Conference (DAC), 2023.
[FPGA’23] Jinming Zhuang, Jason Lau, Hanchen Ye, Zhuoping Yang, Yubo Du, Jack Lo, Kristof Denolf, Stephen Neuendorffer, Alex Jones, Jingtong Hu, Deming Chen, Jason Cong, Peipei Zhou, “CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture,” In Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), 2023. Open-source: https://github.com/arc-research-lab/CHARM. (Over 170 GitHub Stars since 2023)