Muhammad Shaaban Headshot

Muhammad Shaaban

Associate Professor
Department of Computer Engineering
Kate Gleason College of Engineering

585-475-2373
Office Location
Office Mailing Address
RIT Dept. of Computer Engineering 17/2507 83 Lo

Muhammad Shaaban

Associate Professor
Department of Computer Engineering
Kate Gleason College of Engineering

Education

BS, MS, University of Petroleum and Minerals (Saudi Arabia); Ph.D., University of Southern California

Bio

Dr. Muhammad Shaaban obtained his Ph.D. in Computer Engineering from University of Southern California, and his M.S. and B.S. in Electrical Engineering from University of Petroleum and Minerals, Dhahran, Saudi Arabia. His current research focuses on high performance computing and advanced computer architecture, including parallel algorithm design and mapping; micro-heterogeneous computing and cluster computing. His teaching responsibilities include computer architecture and multiple-processor systems. Dr. Shaaban is a senior member of the IEEE.

For more about Dr. Shaaban see his website.

Select publications:

· Dmitri Yudanov, Muhammad Shaaban, Roy Melton, Leon Reznik, 'GPU-based simulation of spiking neural networks with real-time performance and high accuracy,' Proceedings of the 2010 International Joint Conference on Neural Networks (IJCNN 2010), July 18-23, 2010, Barcelona, Spain, pp. 1-8.

· Dmitriy Bekker, Marcin Lukowiak, Muhammad Shaaban, Jean-Francois Blavier, and Paula Pingree, 'Spaceborne Hybrid-FPGA System for Processing FTIR Data,' NASA Tech Briefs, 31(12):30, December 2008.

· Dmitriy Bekker, Marcin Lukowiak, Muhammad Shaaban, Jean-Francois Blavier, and Paula Pingree, 'A Hybrid-FPGA System for On-Board Data Processing Targeting the MATMOS FTIR Instrument,' Proceedings of the IEEE Aerospace Conference, March 2007.

585-475-2373

Personal Links

Currently Teaching

CMPE-550
3 Credits
The course covers various aspects of advanced uniprocessor computer architecture design. Instruction set architecture design alternatives are discussed with emphasis on the Reduced Instruction Set Computer (RISC) architecture. Techniques to enhance CPU performance such as pipelined execution optimizations, conditional branch handling techniques, exploitation of instruction-level parallelism, multiple-instruction issue and dynamic scheduling are studied. Cache, and memory hierarchy design and performance issues are also presented. The design aspects of efficient and reliable input/output systems are also covered.
CMPE-655
3 Credits
The course introduces basic concepts of parallel and high-performance computing and current methodologies and trends in the design and programming of multiprocessor systems. Theoretical models of parallel computing and performance metrics are studied and contrasted with practical parallel system architectures, programming environments, and benchmarking techniques. Parallel architectures are classified according to mode and degree of parallelism, memory organization, and type and typology of interconnection networks used in the design. The suitability of various architectures in meeting demands is studied in depth including the study of representative examples of current commercial machines. Students will complete programming assignments on a parallel computer illustrating practical issues. A review and analysis of a commercial parallel processor system or an active research area is required; written review presented in class.
CMPE-250
3 Credits
This course introduces embedded systems, along with fundamental computer organization, assembly language programming, and mixed language programming with C and assembly. Using a modern microcontroller and embedded systems IDE, such as the ARM Cortex-M0+ and Keil Microcontroller Development Kit, the course covers embedded programming concepts and interface modules, as well as addressing methods, machine instructions, assembler directives, macro definitions, code relocatability, subroutine linkage, data structures, I/O programming, exception processing, and interrupts. Program design techniques necessary to write efficient, maintainable device drivers are considered.