Michael Zuzak Headshot

Michael Zuzak

Assistant Professor

Department of Computer Engineering
Kate Gleason College of Engineering

585-475-2312
Office Location

Michael Zuzak

Assistant Professor

Department of Computer Engineering
Kate Gleason College of Engineering

Bio

Dr. Michael Zuzak is an Assistant Professor in the department of computer engineering at the Rochester Institute of Technology. Dr. Zuzak’s research interests are in hardware security, digital VLSI, and electronic design automation (EDA). His current research explores methods for the design and manufacture of secure, trustworthy, and reliable electronic systems with provable security against reverse engineering, hardware trojan insertion, and side-channel attacks. Prior to his academic career, Dr. Zuzak investigated high-frequency, wide-band digital signal processing system architecture at the U.S. Naval Research Laboratory. He received his Ph.D. in Electrical Engineering from the University of Maryland, College Park.

 

For more information on Dr. Zuzak, visit his website.

585-475-2312

Personal Links

Currently Teaching

CMPE-530
3 Credits
This course will cover the basic theory and techniques of Digital Integrated Circuit Design in CMOS technology. Topics include CMOS transistor theory and operation, design and implementation of CMOS circuits, fabrication process, layout and physical design, delay and power models, static and dynamic logic families, testing and verification, memory and nanoscale technologies. Laboratory assignments and project facilitate in hands-on learning of circuit-level design and simulation, layout and parasitic extractions, pre and post-layout verification and validation, full-custom flow and Synthesis based flow, using industry standard CAD tools.
CMPE-630
3 Credits
This course will cover the basic theory and techniques of Digital Integrated Circuit Design in CMOS technology. Topics include CMOS transistor theory and operation, design and implementation of CMOS circuits, fabrication process, layout and physical design, delay and power models, static and dynamic logic families, testing and verification, memory and nanoscale technologies. Laboratory assignments and project facilitate in hands-on learning of circuit-level design and simulation, layout and parasitic extractions, pre and post-layout verification and validation, full-custom flow and Synthesis based flow, using industry standard CAD tools.