Sonia Lopez Alarcon Headshot

Sonia Lopez Alarcon

Associate Professor
Department of Computer Engineering
Kate Gleason College of Engineering

585-475-4081
Office Location

Sonia Lopez Alarcon

Associate Professor
Department of Computer Engineering
Kate Gleason College of Engineering

Education

BS, Ph.D., Complutense University of Madrid (Spain)

Bio

Dr. Sonia Lopez Alarcon received a B.S. in Physics and M.S. Electronics in from the University Complutense of Madrid, Spain. In her latest college years she worked at Lucent Technologies, Madrid, and Fundetel at Polytechnic University of Madrid, where she became familiar with the design and fabrication process of integrated circuits. In 2003 she started working toward a Ph.D. degree in Computer Engineering at the University Complutense of Madrid, focusing on cache hierarchy in simultaneous multithreaded architectures. In 2004 she started her cooperative research with Professor David H. Albonesi, at the University of Rochester and, later on, at Cornell University. She graduated in 2009, and she joined the Department of Computer Engineering at the Rochester Institute of Technology in the fall of 2009. Her current research interest is on cache optimization, GPU architecture, and heterogeneous hardware solutions. Fro more about Dr. Lopez, see her website.

Selected Publications

  • A phase adaptive cache hierarchy for SMT processors. S. Lopez O. Garnica. D. H. Albonesi, S. Dropsho, J. Lanchares, J. I. Hidalgo. Microprocessors and Microsystems, 2011
  • Reducing Power of Functional Units in High-Performance Processors by Checking Instruction Codes and Resizing Adders. G. Mi–a–a, J.I. Hidalgo, J. Lanchares, J.M. Colmenar, O. Garnica and S. López. IET Computer & Digital Techniques, 2007
  • A Comparison of Sequential and GPU-Accelerated Implementations of B-Spline Signal Processing Operations for 2-D and 3-D Images. A. Karantza, S. Lopez and N. D. Cahill. International Conference on Image Processing Theory, Tools and Applications, October 2012
  • GPU Acceleration of Transmural Electrophysiological Imaging. M. Corraine, S. Lopez, L. Wang. Computing in Cardiology, September 2012
  • Low bandwidth eye tracker for scanning laser ophthalmoscopy. Z. Harvey, A. Dubra, N. cahill. S. Lopez. SPIE Medical Image, February 2012
  • Efficient resource management for Cloud computing environments.A. J. Younge, G.von Laszewski, L. Wang, S. Lopez Alarcon, W. Carithers. Green Computing Conference, August 2010
  • Adaptive Cache Memories for SMT Processors. S. Lopez O. Garnica. D. H. Albonesi, S. Dropsho, J. Lanchares, J. I. Hidalgo. Euromicro conference on Digital system Design, 2010
  • Improving SMT Performance: an Application of Genetic Algorithms to Configure Resizable Caches. J. Díaz and J. Ignacio Hidalgo and Francisco Fernández and Oscar Garnica and Sonia López. Late-Breaking Paper, Genetic and Evolutionary Computation Conference, 2009.

Currently Teaching

CMPE-755
3 Credits
This course will focus on learning and understanding the available hardware options to satisfy the needs of high performance and computational intensive applications. Special attention will be paid to single platform massively parallel devices, their programming and efficient use of the hardware resources. The course will include hands on work with the actual device, lab work, and technical reports and conference paper reading as a relevant source information.
CMPE-350
3 Credits
Provides an understanding of the information transfer and transformations that occur in a computer, with emphasis on the relations between computer architecture and organization. Topics include design levels and their respective primitives, modules and descriptive media, register transfer and micro-operations, basic computer organization and design, central processor organization, control unit and microprogramming, memory organization, input-output organization, computer architecture defining the hardware/software interface, and from architecture to organization (one to many).

Select Scholarship

Journal Paper
Skalicky, S., S. Lopez, and M. Lukowiak. "Performance Modeling of Pipelined Linear Algebra Architectures on FPGAs." Computers and Electrical Engienering 42. (2014): 13. Print.
Lopez, S., et al. "A Phase Adaptive Cache Hierarchy for SMT Processors." Microprocessors and Microsystems, 2011 35. 8 (2011): 683-694. Print.
Published Conference Proceedings
Mansoor, N., et al. "Heterogeneous Photonic Network-on-Chip with Dynamic Bandwidth Allocation." Proceedings of the System On Chip Conference. Ed. Unknown. Las Vegas, NV: n.p., 2014. Print.
Johnstone, B. and S. Lopez. "Satisfying Bandwidth Requirements of GPU Architectures through Adaptive Wavelength Division Multiplexing." Proceedings of the Green Computing Conference. Ed. Unknown. Dallas, TX: n.p., 2014. Print.
Skalicky, S., S. Lopez, and M. Lukowiak. "Mission Control: A Performance Metric and Analysis of Control Logic for Pipelined Architectures on FPGAs." Proceedings of the International Conference on ReConFigurable Computing and FPGAs. Ed. Unknown. Cancun, Mexico: n.p., 2014. Print.
Skalicky, S., et al. "Enabling FPGA support in Matlab based Heterogeneous Systems." Proceedings of the International Conference on ReConFigurable Computing and FPGAs. Ed. Unknown. Cancun, Mexico: n.p., 2014. Print.
Skalicky, S., S. Lopez, and M. Lukowiak. "Distributed Execution of Transmural Electrophysiological Imaging with CPU, GPU, and FPGA." Proceedings of the International Conference on ReConFigurable Computing and FPGAs. Ed. René Cumplido. Cancun, Mexico: IEEE Xplore, 2013. Print.
Fitzgerald, B., S. Lopez, and J. Sahuquillo. "Drowsy Cache Partitioning for Reduced Static and Dynamic Energy in the Cache Hierarchy." Proceedings of the International Green Computing Conference. Ed. Jack Dongarra. Arlington, VA: IEEE Xplore, 2013. Web.
Skalicky, S., et al. "Linear Algebra Computations in Heterogeneous Systems." Proceedings of the Application-Specific system, Architectures and Processors. Ed. Tarek El-Ghazawi. Washington, DC: IEEE Xplore, 2013. Print.
Skalicky, S., et al. "Performance Modeling of Pipelined Architectures on FPGAs." Proceedings of the International Symposium on Applied Reconfigurable Computing. Ed. Pedro C. Diniz. Los Angeles, CA: Springer-Verlag, 2013. Print.
Corraine, M., S. Lopez, and L. Wang. "GPU Acceleration of Transmural Electrophysiological Imaging." Proceedings of the Computing in Cardiology. Ed. Alan Murray. Krakow, Poland: IEEE Xplore, 2012. Print.
Karantza, A., S. Lopez, and N. D. Cahill. "A Comparison of Sequential and GPU-Accelerated Implementations of B-Spline Signal Processing Operations for 2-D and 3-D Images." Proceedings of the International Conference on Image Processing Theory, Tools and Applications. Ed. Mohamed Deriche. Istanbul, Turkey: IEEE Xplore, 2012. Print.
Harvey, Z., et al. "Low Bandwidth Eye Tracker for Scanning Laser Ophthalmoscopy." Proceedings of the SPIE Medical Image. Ed. Norbert J. Pelc. San Diego, CA: n.p., 2012. Print.