Sonia Lopez Alarcon
Sonia Lopez Alarcon
BS, Ph.D., Complutense University of Madrid (Spain)
Dr. Sonia Lopez Alarcon received a Bachelor of Physic degree in Physic and Master degree in Device Physics in 2002 from the University Complutense of Madrid. In her latest college years she worked at Lucent Technologies, Madrid, and Fundetel at Polytechnic University of Madrid, were she became familiar with the design and fabrication process of integrated circuits. In 2003 she started working toward a PhD degree in Computer Engineering at the University Complutense of Madrid, working on cache hierarchy in simultaneous multithreaded architectures. She graduated in 2009, and she joined the Department of Computer Engineering at the Rochester Institute of Technology in the fall of 2009, where she teaches Computing Architecture and Quantum Computing related courses. Her current research interest is on Quantum Computing and heterogeneous hardware solutions. She is particularly interested in the compilation process of quantum circuits, their scalability and resilience to error. For more information, please visit her personal website.
Implementation of Grover’s Algorithm to solve the Maximum Clique Problem. A. Haverly and S. Lopez. International Symposium on VLSI. July 2021
Using Reduced Graphs for Efficient HLS Scheduling. Stephanie Soldavini, Marcin Lukowiak, Sonia Lopez. International Symposium on Circuits and Systems, May 2020
Using Quantum Computers to Study Random Close Packing of Granular Discs, Zachary Gazzillo, Scott Franklin, Sonia Lopez, International Green and Sustainable Computing Conference, October 2019
How Much Cache is Enough? A Cache Behavior Analysis for Machine Learning GPU Architectures, Sonia Lopez, Yash Nimkar, and Gerald Kotas, International Green and Sustainable Computing Conference, October 2018
Alternative Processor within Threshold: Flexible Scheduling on Heterogeneous Systems. S. Karia and S. Lopez. Heterogeneity in Computing Workshop, International Parallel & Distributed Processing Symposium, May 2017
Power Analysis of HLS-Designed Customized Instruction Set Architectures. T. Ananthanarayana, S. Lopez, M. Lukowiak. Reconfigurable Architectures Workshop, International Parallel & Distributed Processing Symposium, May 2017
Designing Customized ISA Processors Using High Level Synthesis. S. Skalicky, T. Ananthanarayana, S. Lopez, M. Lukowiak. International Conference on ReConFigurable Computing and FPGAs. December 2015.
A Parallelizing Matlab Compiler Framework and Run time for Heterogeneous Systems. S. Skalicky, S. Lopez, M. Lukowiak and A. Schmidt. International Conference on High Performance Computing and Communications, HPCC. August, 2015.
Impact of Partitioning Cache Schemes on the Cache Hierarchy of SMT processors. S. Kenyon, S. Lopez and J. Sahuquillo. International Conference on High Performance Computing and Communications, HPCC. August, 2015. Invited paper.
A Unified Hardware/Software MPSoC System Construction and Run-time Framework. S. Skalicky, A. Schmidt, M. French, S. Lopez. Design, Automation and Test in Europe, DATE. March 2015.